Jun 4 2019
A team of over 20 scientists at Tokyo Tech and NEC Corporation has effectively demonstrated a 39 GHz transceiver that could be employed in the next wave of 5G wireless equipment including tablets, smartphones, base stations, and Internet-of-Things (IoT) applications.
CMOS chips on an 18 mm x 163.5 mm evaluation-board. (Image credit: Tokyo Tech)
Although study groups including the present team have so far largely concentrated on developing 28 GHz systems, 39 GHz will be another crucial frequency band for realizing 5G in several regions of the world.
The new transceiver is based on a 64-element (4x16) phased-array design. Its integrated gain phase calibration means that it can enhance beamforming accuracy, and thereby decrease unwanted radiation and improve signal strength.
Fabricated in a typical 65-nanometer CMOS process, the transceiver's economical silicon-based components make it suitable for large-scale production — a main consideration for speedy deployment of 5G technologies.
The scientists demonstrated that the integrated calibration has a very low root-mean-square (RMS) phase error of 0.08°. This figure is an order of magnitude lower than earlier comparable results. While transceivers built to date usually suffer from high gain variation of over 1 dB, the new model has a maximum gain variation of only 0.04 dB over the complete 360° tuning range.
We were surprised to achieve such a low gain variation when actually using the calibration based on our local-oscillator (LO) phase-shifting approach.
Kenichi Okada, Project Leader, Tokyo Tech
Furthermore, the transceiver has the highest equivalent isotropic radiated power (EIRP) of 53 dBm. This is a remarkable indication of the output power of the 64 antennas, the scientists say, especially for cost-effective CMOS implementation.
Indoor testing (under anechoic chamber environments), which involved a one-meter, over-the-air measurement, showed that the transceiver aids wireless transmission of a 400 MHz signal with 64QAM.
By increasing the array scale, we can achieve greater communication distance. The challenge will be to develop the transceiver for use in smartphones and base stations for 5G and beyond.
Kenichi Okada, Project Leader, Tokyo Tech
The paper was presented at the 2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) outer in Boston, Massachusetts, US, as part of the morning session (Session RTu2E) on June 4th, 2019. The paper titled "A 39 GHz 64-Element Phased-Array CMOS Transceiver with Built-in Calibration" by Yun Wang et al., received the best student paper award.