Interfacing to Digital Pressure Sensors for Low Cost, High Performance Digital Pressure (14-bit) and Temperature (11-bit) Outputs

The MEAS series of digital pressure sensors from Measurement Specialties employs the most up-to-date CMOS sensor conditioning circuitry (SSC) for creating a high-performance and digital output temperature (11-bit) and pressure (14-bit) transducer that can fulfill the stringent requirements from OEM customers. The MS45x5DO and 86BSD series is the latest product line from Measurement Specialties to provide digital communication to pressure sensor OEMs.

I2C and SPI Interface Specifications

The I2C interface is a simple 8-bit protocol that utilizes a serial clock line (SCL) and a serial data line (SDA), wherein each device linked to the bus is software addressable and has a unique address. The devices, both master and slave, implement bi-directional bus lines with the help of open-drain output stages and a pull-up resistor in connection with the positive supply voltage. The system configuration (cable and bus clock frequency and capacitance of the circuit) decides the desired pull-up resistor value. It is essential that the SDA and SCL line must have the same capacitive loads.

Figure 1. Both bus lines, SDA and SCL, are bi-directional and therefore require an external pull-up resistor

The I2C address is a seven digit binary value and it is always followed by a write bit (0) or read bit (1). Therefore, the default hexadecimal I2C header to the sensor to get read access is 0x51, 0x6D, 0x8D respectively, depending on the ordering information. The INT/SS pin functions as an interrupt during the programming of an I2C device. The INT/SS pin rises if new output data is ready and falls if during the occurrence of the next I2C communication. Transmission START condition (S) is a unique state on the bus induced by the master to indicate the slaves the start of a transmission sequence.

Figure 2. A HIGH to LOW transition on the SDA line while SCL is HIGH

Transmission STOP condition (P) is a unique state on the bus activated by the master to indicate the slaves the completion of a transmission sequence.

Figure 3. A LOW to HIGH transition on the SDA line while SCL is HIGH

A receiver signals an acknowledge condition following the transmission of each byte (8 bits) over the I2C bus, as shown in Figure 4. If the SDA line is not pulled low by the receiver following the transmission of the 8th bit, the situation is an NACK condition. The missing of an ACK during a slave to master transmission prompts the slave to go into idle mode by terminating the transmission.

Figure 4. Each byte is followed by an acknowledge or a not acknowledge, generated by the receiver

In the I2C protocol, the most significant bit (MSB) is transferred first during data transfer. The I2C header comprises the data direction bit (R/_W) and 7-bit.C device address. The value of the R/_W bit in the header decides the data direction for the remaining data transfer sequence. The I2C master command begins with the 7-bit slave address with the 8th bit = 1 (READ). The sensor serves as the slave and transmits an ACK indicating success. The sensor has four I2C read commands, namely Read_MR, Read_DF2, Read_DF3, and Read_DF4. The structure of the measurement packet of these four I2C read commands is illustrated in Figure 5.

Figure 5. I2C Measurement packet reads I2C Read_DF (Data Fetch)

Following the transmission of the NACK and stop condition by the master, the number of data bytes sent back by the sensor is determined for Data Fetch commands. For the Read_DF3 data fetch command shown in example 3 of Figure 5, the sensor sends back three bytes following the transmission of the slave address and the READ bit by the master.

Following the receipt of the desired number of data bytes, the master transmits the NACK and stop condition to abort the read operation. For the Read_DF4 command shown in example 3 of Figure 5, the master delays the transmission of the NACK condition and keeps on reading an extra final byte for the acquisition of the full corrected 11-bit temperature measurement. In such a situation, the last 5 bits of the final byte of the packet are unnoticed and must be masked off in the application.

The Read_DF2 command, shown in Figure 5, is utilized if there is no requirement for corrected temperature. The master aborts the READ operation following the receipt of the two bytes of bridge data.

The two status bits (Bit 15 and Bit 14) provide a clue of stale or valid data based on their value. A returned value of 00 represents ‘normal operation and a good data packet,’ and a returned value of 10 represents ‘stale data that has been already fetched.’

Status Bits and Diagnostic Features

The table below summarizes The status bits conditions shown by the 2 MSBs (Bit (15:14) of I2C data packet, S(1:0) of SPI data packet of the bridge high byte data are summarized in Table 1.

Table 1. Status Bits Encoding

Status Bits (2 MSB of Output Data Packet) Definition
00 Normal operation. Good data packet
01 Reserved
10 Stale data. Data has been fetched since last measurement cycle
11 Fault detected

The on-board diagnostic features of the SSC ensure the efficient operation of the system in many mission-critical applications. All diagnostics are determined in the coming measurement cycle and accounted in the subsequent data fetch.

There is no change in the diagnostic status bits even after reporting a diagnostic. The diagnostic status bits will change only after fixing the cause of the diagnostic and performing a power-on-reset. The I2C interface parameters are listed in Table 2.

Table 2. I2C interface parameters

PARAMETERS SYMBOL MIN TYP MAX UNITS
SCLK CLOCK FREQUENCY fSCL 1GG 400 KHz
START CONDITION HOLD TIME RELATIVE TO SCL EDGE tHDSTA G.1 uS
MINIMUM SCL CLOCK LOW WIDTH1 tLOW G.6 uS
MINIMUM SCL CLOCK HIGH WIDTH1 tHIGH G.6 uS
START CONDITION SETUP TIME RELATIVE TO SCL EDGE tSUSTA G.1 uS
DATA HOLD TIME ON SDA RELATIVE TO SCL EDGE tHDDAT G uS
DATA SETUP TIME ON SDA RELATIVE TO SCL EDGE tSUDAT G.1 uS
STOP CONDITION SETUP TIME ON SCL tSUSTO G.1 uS
BUS FREE TIME BETWEEN STOP AND START CONDITION tBUS 2 uS

1Combined LOW AND HIGH Widths must EQUAL or EXCEED minimum SCL period.

I2C timing diagram is depicted in Figure 6.

Figure 6. I2C Timing diagram

SPI Interface Specification

During the transfer of SPI, a general-purpose synchronous serial interface, data transmission and receipt is concurrently and serially shifted out. The transfer and sampling of the data on two serial data lines is synchronized by a serial clock line.

The communication of SPI devices is through a master-slave relationship. When more than one slave is engaged, more effort and more hardware resources are required for SPI due to its lack of built-in device addressing when compared to I2C.

Nevertheless, when compared to I2C, SPI is simple and efficient in point-to-point (single master, single slave) applications due to the lack of device addressing, which minimizes overhead.

SPI Read_DF (Data Fetch)

Data change will be there in the SPI interface after the falling edge of SCLK. Sampling MISO must be done by the master on the rise of SCLK. The entire output packet is 4 bytes, of which first comes the high bridge data byte and then the low bridge data byte. Then 11 bits of corrected temperature (T[10:0]) are transmitted.

The last 5 bits of the final byte are unnoticed and must be masked off in the application. It is possible to abort the read after the 2nd byte to get the corrected bridge value. Moreover, the read can be aborted after reading the 3rd byte to get the corrected temperature but only at an 8-bit resolution. SPI output packet with falling edge SPI polarity is shown in Figure 7.

Figure 7. SPI Output packet with falling edge SPI_Polarity

The SPI interface parameters are given in Table 3.

Table 3. SPI interface parameters

PARAMETERS SYMBOL MIN TYP MAX UNITS
SCLK CLOCK FREQUENCY fSCL 50 800 KHz
SS DROP TO FIRST CLOCK EDGE tHDSS 2.5 uS
MINIMUM SCL CLOCK LOW WIDTH1 tLOW 0.6 uS
MINIMUM SCL CLOCK HIGH WIDTH1 tHIGH 0.6 uS
CLOCK EDGE TO DATA TRANSITION tCLKD 0 0.1 uS
RISE OF SS RELATIVE TO LAST CLOCK EDGE tSUSS 0.1 uS
BUS FREE TIME BETWEEN RISE AND FALL OF SS tBUS 2 uS

1Combined LOW and HIGH widths must EQUAL or EXCEED minimum SCLK period.

The SPI timing diagram is illustrated in Figure 8.

Figure 8. SPI Timing diagram

This information has been sourced, reviewed and adapted from materials provided by Measurement Specialties.

For more information on this source, please visit Measurement Specialties.

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