Intelligence in 3D Accelerometer Sensors

Sensors produce raw signals which must be processed before being of value. The consumption of processing algorithms is becoming dominant with the advent of the new generation of deep-ultra-low power sensors (µW consumption range), and so it is limiting for low-power applications.

This article demonstrates that by combining CSEM's algorithmic and ultra-low power know-how, it is possible to supply the intelligent algorithmic layer without affecting the already negligible consumption of sensors. The study is presented for 3D accelerometers sensors and activity tracking processing algorithms.

Over recent years the power consumption of 3D accelerometers has been decreasing continuously from more than 100 µW (e.g., ADXL345) to below 4 µW (e.g., ADXL362) and this trend is still on-going.

On the other hand, related processing algorithms that run on standard microcontrollers still consume in the order of 100 µW, overwhelmingly impacting the power budget. The goal of this study is to bridge this gap for a particular case relevant to the market: physical activity tracking based on inertial sensors (e.g., 3D accelerometers).

The booming industry of wearables (e.g., smart-textiles, smartwatches) where the decreased consumption results in extended autonomy and so, increased user comfort would benefit massively from these results.

For low-power wearable devices relying on inertial sensors, CSEM has a long history of algorithm design, development, and implementation. The following might be highlighted among them:

1. Activity profiling
2. Kinetic analysis
3. Gait analysis
4. Energy expenditure
5. Fall detection
6. Swimming performance monitoring

The main aim is to turn a simple 3D accelerometer into a smart sensor by adding such intelligent algorithmic layers with negligible overall consumption overhead. Five alternatives have been considered and are outlined below, with the results summarized in Table 1.

Table 1. Activity tracking algorithm consumption and flexibility. Source: CSEM 

# Hardware Supply Algorithm Sensor Flexibility
1 CortexM0 1.8 V 90 µW 4 µW Yes
2 icyflex2 1.0 V 16 µW 4 µW Yes
3 Accelerator 1.0 V 1 µW 4 µW No
4 Accelerator 0.5 V 0.1 µW 4 µW No
5 icyflex2 0.5 V 0.8 µW 4 µW Yes


The reference design is option 1. To run the activity tracking algorithm software it utilizes an ARM’s Cortex-M0 microcontroller embedded into a Nordic BLE transmitter (NRF51822). Power consumption is estimated to 90 µW.

CSEM's low-power icyflex2 microcontroller [7] implemented in standard 55 nm bulk technology (at 1 V nominal voltage) is used in Option 2. Power consumption is estimated at 16 µW and when compared to the 4 µW sensor consumption, is still too high.

Option 3 is to design a dedicated hardware accelerator for the activity tracking algorithm by utilizing the same standard 55 nm technology. Power consumption decreases to 1 µW, which already, is less than the sensor consumption. Depending on the application power budget it could already be interesting.

Option 4 is to take it one step further for the dedicated hardware accelerator design and utilize sub-threshold voltage design on a specially tailored MIFS Deeply Depleted Channel (DDC [8]) 55 nm technology (at 0.5 V supply voltage). The power consumption is estimated to more than one order of magnitude lower than the sensor, at 0.1 µW.

Option 5 is based on option 4’s sub-threshold conditions and technology but the algorithm is performed on an icyflex2 microcontroller [9]. In this instance, running the algorithm draws 0.8 µW, similar to that of the dedicated hardware accelerator at nominal voltage, but with the benefit of a microcontroller’s flexibility.

So, the algorithm may be tailored to the application requirements or refined during the product lifetime. As predicted, dedicated hardware accelerators exhibit the lowest power for adding higher level intelligence, like activity tracking to a 3D accelerometer with up to 100-1000x power gain compared to the reference design, only impacting the sensor power budget slightly.

Yet, comparable power levels are attained when implementing the algorithm on an icyflex2 general purpose microcontroller due to CSEM's know-how in sub-threshold design, yielding the best of the power-flexibility trade-off.


Produced from materials originally authored by M. Pons Solé, E. M. Calvo, R. Cattenoz, R. Delgado-Gonzalo and S. Emery from CSEM.


[1] R. Delgado-Gonzalo, et al., "Learning a Physical Activity Classifier for a Low-power Embedded Wrist-located Device," IEEE BHI (2018).

[2] M. Bertschi, et al., "Accurate Walking and Running Speed Estimation Using Wrist Inertial Data," IEEE EMBC (2015).

[3] R. Delgado-Gonzalo, et al., "Real-time Gait Analysis with Accelerometer-based Smart Shoes," IEEE EMBC (2017).

[4] R. Delgado-Gonzalo, et al., "Human Energy Expenditure Models: Beyond State-of-the-art Commercialized Embedded Algorithms," DHM (2014).

[5] C. Moufawad el Achkar, et al., "Real-time Fall Detection Using Smartwatches," EU Falls Festival (2018).

[6] R. Delgado-Gonzalo, et al., "Real-time Monitoring of Swimming Performance," IEEE EMBC (2016).

[7] J.-L. Nagel, et al., "The icyflex2 Processor Architecture", CSEM Scientific and Technical Report (2009).

[8] K. Fujita, et al., "Advanced Channel Engineering Achieving Aggressive Reduction of VT variation for Ultra-low-power Applications," IEEE IEDM (2011).

[9] M. Pons, et al., “A 0.5V 2.5 μW/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13nW/kB SRAM Retention in 55 nm Deeply-Depleted Channel CMOS,” IEEE CICC (2019)

This information has been sourced, reviewed and adapted from materials provided by CSEM.

For more information on this source, please visit CSEM.


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