With chipmakers keen to move toward 5 nm manufacturing, it’s evident that traditional scaling is not extinct but continuing along with other technologies. The industry is exploring scaling enabled by 3D architectures such as die stacking and the stacking of miniature geometry wafers. Interconnect scaling also forms a part.
This year’s Scaling Technologies TechXPOT at SEMICON West (Scaling Every Which Way!—Thursday, July 12th, 2:00 PM-4:00 PM) will provide an update on the development of scaling and illustrate how the different players (foundry, fabless, IDM, and application developers) are racing for innovation leadership. As an introduction to the event, SEMI interviewed speakers to provide insights on critical scaling trends.
Challenges for Gate-All-Around (GAA) and FinFET Devices
During the processing of GAA devices, there are ‘non-line-of-sight’ hidden features that are difficult to control and characterize and may also lead to new defect mechanisms that would impact yield, and possibly product reliability.”
Diederik Verkest, imec Distinguished Member of Technical Staff, Semiconductor Technology and Systems
Typical performance boosters for gate-all-around (GAA) FETs and FinFETs include lower parasitic capacitance, lower access resistance, and stress. “However, one specific performance booster that only applies to GAA is the reduction of the spacing between the vertical wires or sheets,” says Diederik Verkest, imec distinguished member of technical staff, Semiconductor Technology and Systems. “This reduces parasitic capacitance without affecting drive current and hence benefits both performance and power.” He further observes that imec showed the first stacked gate-all-around (GAA) devices in scaled nodes. “In fact, we are the only ones that published working circuits— ring oscillators in a scaled node using industry-standard processes—in our case replacement metal gate (RMG), and embedded in situ doped source/drain (S/D) epitaxy.”
“There are two elements of the stacked GAA architecture that need to be addressed,” says Verkest. “The first is that this architecture uses epitaxially-grown layers of Si and SiGe to define the device channel. The use of grown materials for the channel and the lattice mismatch between the two materials represent a departure from the traditional fabrication of CMOS devices, so the industry needs to develop and gain confidence in novel metrology that allows for good control of the layers and also proves their low defectivity.” The second aspect is the three-dimensional (3D) nature of the GAA devices. “During the processing of these devices, we have ‘non-line-of-sight’ hidden features that are difficult to control and characterize and may also lead to new defect mechanisms that would impact yield, and possibly product reliability.”
A new device architecture beyond FinFET is required to provide a full technology node scaling benefit (i.e., density, power, and performance) at 5 nm and 3 nm.”
Huiming Bu, Director, Advanced Logic/Memory Research—Integration and Device, IBM Research, Semiconductor Group
According to Huiming Bu, naming of technology nodes has been used widely for marketing strategies in “foundry land,” but the designations have lost much of their connotation as technology scaling differentiators. “That said, when it comes to technology innovation and value proposition, IBM, in conjunction with Samsung and GLOBALFOUNDRIES, has developed the GAA NanoSheet transistor for 5 nm to provide a full technology node scaling benefit in density, power, and performance,” says Bu (Figure 1). Bu explains that the main parameters for intrinsic device optimization when scaling to the 3 nm node are the NanoSheet width for improved electrostatic features, and the number of sheets for boosted current density. Also essential are strain engineering for carrier transport improvement, and interconnect innovations for parasitic RC reduction. “Beyond that, the industry needs to look into something different, something more disruptive.”
Figure 1. TEM cross-section of stacked NanoSheet transistors. Source: IBM Research
Materials challenges are also an issue as the industry transitions to 5 nm and below. “We see increasing complexity in the material systems that are being used,” explains Verkest. One instance he quotes in scaled FinFET or GAA technologies is the employment of two to three layers of different materials—usually metals such as TiN—to which small quantities of other elements are incorporated to set device features such as the threshold voltage. “At the same time, the requirements for the thickness of these materials, driven by gate dimensions for example, or the distance between the wires, are increasingly challenging.” Other instances of materials challenges are the use of two to three various types of insulators in the middle-of-the-line, each with varying etch contrasts. “We use novel materials such as carbon-containing oxides or oxynitrides that have lower dielectric constants in order to boost the performance of circuits,” he says, observing that the materials list “is quite long.”
A number of critical dimensions in transistors at cutting-edge technology nodes have already attained a few monolayers of atoms, driving expectations for modernization at the material level for transistor scaling, Bu states. “The other argument is that there is a growing gap between computing demand and the slowdown of technology advancement driven by conventional scaling,” says Bu. One trend that resolves this gap is incorporating more computing functions that make the technology solution more modular, which obviously leads to the integration of more materials for more applications. Bu warns, however, that adding new materials in semiconductor technology has always been tough. “It takes many years of R&D to reach this implementation point, if it ever happens. So, do we need new materials when the industry moves to 5 nm and 3 nm? Yes, though I expect new material implementation to be a lot faster in interconnect and packaging at these nodes rather than intrinsic to the transistor.”
Challenges in Developing Atomic-Level Processes
There will be issues in formulating atomic-level processes used in scaling, such as atomic layer depositions (ALD) and atomic layer etches, observes Verkest. “These classes of processes are both required to handle the scaled dimensions at the 5 nm and 3 nm nodes, and also the 3D nature of the scaled technologies— and here we are talking about logic and memories,” Verkest says. “With respect to depositions, we would need to develop thermal ALD processes (not plasma-based) that enable accurate and conformal depositions in non-line-of-sight structures.” Adhesion and wetting, throughput, and smoothness would also have to be looked into. “Longer term, these processes need to facilitate selectivity and self-alignment to address gap-fill challenges in highly scaled structures,” he says. Other apprehensions he notes in relation to atomic layer etches are selectivity to numerous materials, and fidelity needs that increase the requirements for metrology accuracy. “Throughput is also a concern.”
Bu feels that a new device architecture beyond FinFET is needed to provide a complete technology node scaling benefit (i.e., power, density, and performance) at 5 nm and 3 nm. “Beyond 3 nm, we may need to continue the transistor scaling in the vertical direction and start to stack them together,” Bu says. He also mentions the necessity for parasitic RC reduction in the interconnect to exploit the intrinsic transistor advantage at the circuit and chip levels. “We see a lot of opportunity in atomic-level processes, especially in atomic layer etch and selective material deposition, to address these challenges in the transistor and the interconnect.”
This information has been sourced, reviewed and adapted from materials provided by SEMI.
For more information on this source, please visit SEMI.