Inspection Challenges with 5nm

At SEMICON West this year (Scaling Every Which Way!—Thursday, July 12th, 2018, 2:00 pm–4:00 pm), the Scaling Technologies TechXPOT will explore conventional scaling as the industry’s inclination is toward 3 nm and further, and also technologies that enable die stacking, 3D architectures, and interconnect scaling.

Moreover, the session will offer an update on the way different players (fabless, foundry, application developers, and IDM) are competing for innovation leadership. As an introduction to the event, SEMI asked Priya Mukundhan, director, Technology Development and Applications, at Rudolph Technologies, as well as a speaker at the TechXPOT, to present her understanding of the difficulties associated with metrology and inspection.

Priya Mukundhan, director, Technology Development and Applications, Rudolph Technologies

Priya Mukundhan, director, Technology Development and Applications, Rudolph Technologies

SEMI: What are the significant challenges that have to be overcome to offer the kind of metrology and inspection solutions that will be required by the industry while pursuing scaling—in all its forms (such as conventional, interconnect, 3D ICs, and different transistor designs)—at 5 nm and subsequently at 3 nm?

Priya Mukundhan: Regarding metrology required to scale FinFETs, following are the most important aspects:

  • Gate critical dimension (CD) at the fin sidewall, gate height, gate profile
  • Stress measurement in the fin
  • Fin CD, height, and profile
  • Composition in thin film and interface
  • Dopant profiles

At present, these challenges are being dealt with using in-line CD scanning electron microscopy (CD-SEM), CD solutions, and CD atomic force microscopy (CD-AFM), together with optical critical dimension (OCD) measurements. No single technology exists with the ability to take all of these measurements, and ascertaining that the apt solution is application-dependent.[1]

Challenges in carrying out the scaling and inspection are as follows:

  • Defects smaller than those located at the 20 nm node cannot be detected through bright-field inspection due to its lack of sensitivity
  • Detection of sidewall cracks in packaging
  • Although electron-beam inspection tools can be used to detect defects equal to or smaller than 5 nm, such single-electron-beam inspection systems are prohibitively slow and cannot fulfill the high-volume manufacturing (HVM) requirements for the inspection of defects
  • Detection of voids in 3D SiP structures, front and rear-side inspection
  • Buried defects

SEMI: Can you come up with an outline of the R&D roadmap for metrology/inspection tools that you observe emerging to achieve 3 nm?

PM: At present, hybrid metrology is in use, specifically for CD metrology. In order to assist in the development efforts, methods that offer complementary information and even those that remove uncertainties will be needed.

Scientists at imec[2] have begun the exploration of technology combinations to understand the functioning of new structures. Certain outcomes of the imec’s study are as follows:

  • When transmission electron microscopy (TEM) is used in combination with scanning probe microscopy (SPM), it turns out to be a unique way of imaging integrated with a functional analysis capability
  • In situ SPM could prospectively find out composition (SIMS) and also functional properties (electrical)
  • Fast Fourier transform scanning spreading resistance microscopy (FFT-SSRM) is an innovative technology that involves measuring carrier profiles in semiconductors. This overcomes the existing SSRM drawbacks of signal distortions caused by parasitic resistances while measuring on small volumes such as nanowires and FinFET
  • Multi-electron beam inspection can be applied for HVM for too smaller sensitivity

SEMI: What are the impacts on metrology and inspection beyond 3 nm? What are the types of tools that will be required by that point in time?

PM: There are various distinctive transistor options that have been recognized by leading-edge wafer fabs and consortia looking beyond the 5 nm node roadmap.[3,4] Certain options on the table are as follows:

  1. Extension of the existing FinFET in terms of gate-all-around FET
  2. Developing them with innovative materials through the addition of ferroelectrics (such as negative capacitance FET (NC-FET))
  3. Vertical nanowires and nanosheet FETs
  4. Complementary FET

These probabilities give rise to new challenges and mandate the characterization at the material level. Moreover, collectively, the industry must rethink the concept of composition at the nanoscale. This could turn out to be the start of a tendency toward array-based metrology, that is, performing measurements on an array of devices to collect statistically significant data.[2]

With respect to metrology requirements at 3 nm, it is premature to decide the kind of tools that would be required only for R&D and the number of tools that would be required to be extended to high-volume manufacturing (HVM). From an inspection point of view, there will be a persistent migration toward computer-aided design (CAD)-based inspection, and also with the potential to handle large image data sets (petabyte, big data). Moreover, inspection algorithms should be enhanced, in addition to improved staging for improved image stitching.


  1. Bunday, E. Solecky, A. Vaid, A. F. Bello, X. Dai, “Metrology capabilities and needs for 7 nm and 5 nm logic nodes,” Proc. Of SPIE, Vol. 10145, 101450G, pp. 1–41, 2017.
  2. Imec roadmap and imec magazine.
  3. Intel roadmap.

This information has been sourced, reviewed and adapted from materials provided by SEMI.

For more information on this source, please visit SEMI.


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