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New Sensor Interfaces Cut Down Design Effort and Reduce Circuit Complexity

A novel category of Digital-to-Analog (DAC) and Analog-to-Digital Converters (ADC) has been invented by the Green IC research group in the Department of Electrical and Computer Engineering at the National University of Singapore’s (NUS) Faculty of Engineering.

Catastrophic failure is replaced by graceful resolution degradation in the novel class of conventional data converters invented by the NUS researchers. (Image credit: National University of Singapore)

These innovative converters can be fully designed using a completely automated digital design methodology because of their fully digital architecture.

In contrast to conventional analog architectures and methodologies, the design turnaround time for these innovative sensor interfaces is decreased from months to hours. The substantial reduction in the design effort is extremely advantageous in cost-sensitive silicon systems, for example, sensors for the Internet of Things (IoT).

Furthermore, the innovative data converter architecture is not very complex and has minimal silicon area, thus reducing the manufacturing cost by at least 30 times, when compared to traditional designs.

Innovative data converters such as these also display the unparalleled potential to gracefully degrading the signal fidelity when there are extensive fluctuations in its supply voltage or clock frequency. These fluctuations are typical in energy-harvested IoT sensors, because the power harnessed from the nearby environment (for example, solar cell) is extremely unpredictable.

In turn, this enables uninterrupted sensor signal monitoring even under adverse harvested power conditions, and without voltage control. By contrast, conventional data converters experience disastrous degradation of resolution when the supply voltage is lower than its minimum rated value Vmin (or the frequency surpasses its maximum rated value), thus necessitating power-hungry circuits for regulating frequency and voltage.

The study was performed in partnership with Associate Professor Paolo Crovetti from the Politecnico di Torino in Italy, and is backed by the Singapore Ministry of Education and the EU Commission.

Smaller Sensor Interfaces, Simpler and Faster to Design

Our research transforms the traditionally analog and mostly-manual design of data converters into fully-automated digital design, reducing the silicon area by an order of magnitude and the design time by two orders of magnitude, allowing semiconductor companies to be cost-competitive while reaching markets faster.

Massimo Alioto, Study Team Leader and Associate Professor, Department of Electrical and Computer Engineering, Faculty of Engineering, National University of Singapore

He added, “Being digital, our sensor interfaces are effortlessly ported across manufacturing technologies and applications, and can be immersed in digital circuits to avoid the traditional effort required by their integration on the same silicon chip.”

The concept was demonstrated by the NUS researchers using numerous silicon chips that implemented both DACs and ADCs with a very low area. As an example, a 12-bit DAC developed with 40 nm standard CMOS technology has been validated with an area equivalent to the diameter of a strand of human hair. Its intrinsic tractability for technology scaling makes it contract by about another 32 times upon being implemented in the currently finest technology (7 nm).

Simultaneously, the NUS invention has been demonstrated to facilitate data converters with high resolutions (up to 16 bits), while realizing design compactness and simplicity.

Our team has introduced a new design paradigm that pushes us closer to the ultimate vision of inexpensive, technology-scalable and ultra-compact IoT devices.

Dr Orazio Aiello, Visiting Research Fellow, Department of Electrical and Computer Engineering, Faculty of Engineering, National University of Singapore

Unprecedented Robustness Brings Additional Benefits at the System Level

The NUS innovation further streamlines integrated system design, exploiting the unparalleled ability to endure very large voltage and frequency fluctuations, thus relaxing the accuracy demands in frequency and voltage generation.

In fact, traditional data converters that operate at a supply voltage lower than its minimum rated value (or excessive clock frequency) experience disastrous failure, and hence do not execute their envisioned function.

In contrast, the novel data converters invented by the NUS researchers show graceful degradation of the resolution and signal fidelity when clock frequency or supply voltage surpasses its predefined range.

As an example, a DAC engineered for 1 V was shown to accurately operate at half this voltage, while its resolution was degraded by only 1 bit when the supply voltage was decreased by a considerable 0.3 V.

The capability of having graceful resolution degradation under voltage and frequency overscaling suppresses the need for complex circuit solutions that accurately regulate the supply voltage and the clock frequency being utilised by data converters. In other words, our data converters are simpler to design, and also simplify the system that they are employed in.

Massimo Alioto, Study Team Leader and Associate Professor, Department of Electrical and Computer Engineering, Faculty of Engineering, National University of Singapore

Next Steps

At present, the NUS team is working on an innovative paradigm that converts conventionally analog and design-intensive silicon sub-systems into digital standard cell-based designs that are aided by completely automated design flows, pushing the limits of classical digitally assisted design. In this study, a number of major sub-systems such as voltage and current references, oscillators, amplifiers, and many others were utilized.

The researchers aim to completely revolutionize the way integrated systems are engineered, allowing ultra-compact, ultra-rapid, and technology-portable design of complete systems.


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