Delft University of Technology (TU Delft) and nanoelectronics research center imec, today presented 3D-COSTAR, a new test flow cost modeling tool for 2.5/3D stacked integrated circuits (ICs).
3D-COSTAR aims to optimize the test flow of 3D stacked ICs (SICs), taking into account the yields and costs of design, manufacturing, packaging, test, and logistics.
Due to its many high-precision steps, semiconductor manufacturing is defect-prone. Consequently, every IC needs to undergo electrical tests to weed out defective parts and guarantee outgoing product quality to the customer. For TSV-based 2.5D- and 3D-SICs that typically contain complex die designs in advanced technology nodes, testing is even more critical. In addition, there are many possible test moment in their manufacturing flow: pre-bond (before stacking), mid-bond (on a partial stack), post-bond (on a completed stack), and final testing (on a packaged device). Although testing is expensive, filtering out the bad components in an early stage is critical to save costs later on in the production process.
“There is not a ‘one-size-fits-all’ test flow that covers all stacked-die products. The test flow needs to be optimized based on yield and cost parameters of an individual product and that is a complex optimization problem,” stated Dr. Said Hamdioui, Associate Professor at TU Delft. “And different test flows, executed after manufacturing, may require different design-for-test features, which need to be incorporated in the various dies during their early design stages.”
3D-COSTAR uses input parameters that cover the entire 2.5D-/3D-SIC production flow: 1) design; 2) manufacturing; 3) test; 4) packaging; and 5) logistics. It is aware of the stack build-up (2.5D versus 3D, multiple towers; face-to-face or face-to-back) and stacking process (die-to-die, die-to-wafer, or wafer-to-wafer). The tool produces three key analysis parameters: 1) product quality, expressed as defect level (test escape rate) in DPPM (defective parts per million); 2) overall stack cost; and 3) breakdown per cost type.
“3D-COSTAR has proven to be a crucial tool to analyze the many complex trade-offs in 3D test flows, in terms of both cost and DPPM,” said Erik Jan Marinissen, Principal Scientist at imec. “Among others, we have used 3D-COSTAR to determine when pre-bond testing of the interposer in 2.5D-SICs pays off and what its maximum-allowed test cost can be. In some cases, the overall stack cost reduction amounts to 40%, showcasing that upstream testing can help avoid downstream costs. The tool also demonstrated under which circumstances mid-bond testing (on partially-completed stacks) can be avoided without compromising a high stack yield.”
“Together with imec, Cascade Microtech has recently demonstrated the feasibility of direct probing large-array fine-pitch micro-bumps to avoid the usage of dedicated pre-bond pads,” stated Ken Smith, Principal Engineer, Cascade Microtech, Inc. (of Beaverton, Oregon, USA). “Analysis with 3D-COSTAR clearly showed up to 50% overall cost benefit of doing microbump probing using an advanced probe cell such as was demonstrated with Pyramid Probe® RBI technology on our CM300 probe station.”
About Delft University of Technology
Delft University of Technology’s (TU Delft) unique social position, as set out in 'Challenging the Future', means that our programmes are designed with the engineers of the future in mind. It is these young engineers that will develop novel solutions to the global challenges of the year 2040. The world's population is expected to grow to 9 billion people by 2050, but as yet the living standards of the vast majority of the world's population still lag far behind those of the rich developed world. Rising living standards in the developing world represents the greatest challenge of the future and will unleash complex issues. Increasing energy consumption and dwindling natural resources, a worsening climate problem, globalisation, structural poverty, urbanisation, war and international migration would all seem to be in store.
In the context of such developments, the Faculty of Electrical Engineering, Mathematics and Computer Science (EEMCS) has a clear vision of its role and responsibilities. Electrical engineering, mathematics and computer science will make vital contributions to global welfare, well-being, and security. ICT will play an essential role in our future society. It will be a driver of ever greater globalisation, connecting a world which will become totally networked at all possible levels.
Expanding virtualisation will also lead to new paradigms. The Faculty of EEMCS will make a real contribution to developing sustainable products and systems and address the challenges of energy production, storage and distribution.
Imec performs world-leading research in nanoelectronics. Imec leverages its scientific knowledge with the innovative power of its global partnerships in ICT, healthcare and energy. Imec delivers industry-relevant technology solutions. In a unique high-tech environment, its international top talent is committed to providing the building blocks for a better life in a sustainable society. Imec is headquartered in Leuven, Belgium, and has offices in Belgium, the Netherlands, Taiwan, US, China, India and Japan. Its staff of more than 2,000 people includes more than 650 industrial residents and guest researchers. In 2012, imec's revenue (P&L) totaled 320 million euro.
Imec is a registered trademark for the activities of IMEC International (a legal entity set up under Belgian law as a "stichting van openbaar nut”), imec Belgium (IMEC vzw supported by the Flemish Government), imec the Netherlands (Stichting IMEC Nederland, part of Holst Centre which is supported by the Dutch Government), imec Taiwan (IMEC Taiwan Co.) and imec China (IMEC Microelectronics (Shanghai) Co. Ltd.) and imec India (Imec India Private Limited).
Hanne Degans, External Communications Officer, T: +32 16 28 17 69, Mobile : +32 486 06 51 75, [email protected]
Said Hamdioui, Associate Professor, T: +31 15 278-3643, Mobile: +31 62 880-2494, [email protected]