Sony Announces Investment to Increase Stacked CMOS Image Sensor Production Capacity

Sony Corporation ("Sony") today announced that it plans to invest in Sony Semiconductor Corporation's Nagasaki Technology Center ("Nagasaki TEC") and Kumamoto Technology Center ("Kumamoto TEC") from the second half of the fiscal year ending March 31, 2015 ("FY14") through the first half of the fiscal year ending March 31, 2016 ("FY15"), to increase its production capacity for stacked CMOS image sensors.^*1

This investment is primarily intended to reinforce Nagasaki TEC's layering process^*2 production capabilities, as well as Kumamoto TEC's mastering process^*3 facilities.

On January 29, 2014, Sony announced its plans to establish and invest in Yamagata Technology Center ("Yamagata TEC") as a facility mainly conducting the mastering process. The current investment is expected to enable Sony to complete subsequent stages of production, including the layering process, at Nagasaki TEC on semiconductor chips that have undergone the mastering process at Yamagata TEC, providing Sony with a fully integrated production system for stacked CMOS image sensors.

This investment forms part of Sony's mid - to long-term plan to increase its total production capacity for image sensors to approximately 75,000 wafers per month,^*4 and is expected to increase the current capacity of approximately 60,000 wafers per month to approximately 68,000 wafers per month in August 2015.

Stacked CMOS image sensors deliver superior image quality and advanced functionality, together with compact size. Demand for these image sensors is anticipated to further increase, particularly within the expanding market for mobile devices such as smartphones and tablets. Sony intends to bolster its manufacturing capacity for stacked CMOS image sensors, and further strengthen its integrated supply operations, and to thereby reinforce its leading market position.

The total investment amount is expected to be approximately 35 billion yen, comprising approximately 9 billion yen (Nagasaki TEC: approximately 3 billion, Kumamoto TEC: approximately 6 billion) to be carried out in FY14, and approximately 26 billion yen (Nagasaki TEC) to be carried out in FY15. Of this, the amount to be invested in FY14 (approximately 9 billion yen) was included in the forecast of capital expenditure for semiconductors in the current fiscal year (approximately 65 billion yen) announced on May 14, 2014.

Notes
^*1 : CMOS image sensors layer, in a stacked structure, the pixel section, containing back-illuminated structure pixels, onto chips containing the circuit for signal processing, in contrast to the supporting substrates used in conventional back-illuminated CMOS image sensors.
^*2 : The layering process refers to the layering semiconductor chips containing back-illuminated structure pixels with semiconductor chips containing the circuit for signal processing.
^*3 : The mastering process refers to the manufacture of photodiodes and wiring processes for stacked CMOS image sensors.
^*4 : This total production capacity (300mm wafer basis) includes the output of foundry operations to which Sony outsources a part of the manufacturing process. For the purposes of calculating total production capacity, the capacity of 200mm wafer production lines in Kagoshima Technology Center and Nagasaki TEC is converted to the new 300mm wafer production capacity basis.

Source: http://www.sony.net/